The present invention relates to an image processing LSI (Large-Scale Integrated circuit) for performing graphics computations and to an image processing program that operates using the image processing LSI. Particularly, the present invention is suitable for use in limiting the storage capacity of the work area of a RAM (Random Access Memory) used for graphics computations.
When a graphics drawing process is performed by an image processing LSI, drawing data of many line segments and simple figures are synthesized to obtain a desired image and display the obtained image on a display device. The line segments and figures, which are elements of a drawing, are expressed by parameters called vector data that includes, for example, a curvature and the coordinates of vertex or other feature point. In graphics computations, for each of many line segments and figures forming an image within a frame, the drawing data to be drawn on each pixel within the frame is calculated from the vector data, and the drawing data of all the line segments and figures are combined in a frame buffer to calculate display data to be displayed on the display device on an individual frame basis. The display data represents the luminance or the luminance and color difference of each of three primary colors and is stored in the frame buffer.
An image processing device for performing the above-described graphics drawing process is generally configured by disposing a ROM (Read Only Memory) and a RAM external to the image processing LSI. The external ROM stores the vector data. The external RAM is allocated as the frame buffer. The drawing data, which is intermediate data in graphics computations, is also stored in a work area defined in the external RAM.
A technology disclosed in Japanese Unexamined Patent Publication No. 2011-158951 suppresses an increase in memory usage when a rasterization process is performed by a plurality of arithmetic elements. When rasterizing the intermediate data that is generated on an individual band basis in accordance with page description language data, the disclosed technology generates a plurality of segmented areas by segmenting a band, which has a plurality of cores (arithmetic elements) and forms each set of intermediate data, into a plurality of sections, and assigns the segmented areas to the individual cores to perform the rasterization process.